USB 3.0 Host Controller
Overview:

Sibridge's USB 3.0 Host Controller is a high performance, low gate count, xHCI compliant semiconductor IP designed for SuperSpeed USB host implementations in ASIC or Structured ASIC and engineered for 130 nm process nodes and smaller geometries. The controller implements all of the digital layers defined by the USB 3.0 Specification and is fully backward compatible with USB 2.0. The controller includes multiple user interfaces options including AMBA 2 AHB. 



Feature:  
  • Complies with the Superspeed USB 3.0 Specification, Revision 1.0
  • Complies with xHC specification , Revision 0.96Supports 64-bit data path 
  • Optional Asynchronous clocking between Core and user interface logic (CDC)Up to 16 IN and OUT Endpoints 
  • Includes Physical, Link, and Protocol layers 
  • Supports Bulk with streaming, Control, and Isochronous Endpoints
  • Complies with the USB Revision 2.0 Version specification UTMI+ level3 transreceiver with optional ULPI link wrapper


 


  • Verilog Source code with lint checking
  • Verilog functional testbench and associated documentation
  • Design documentation