|
UART Verification IP provides an smart way to verify the UART component of a SOC or a ASIC. The Sibridge UART Verification IP is fully compliant with standard UART 16550 Specification and provides the following features.
UART VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
Features
- Fully compatible with 16550
- Transmit and receive commands allow the user to transmit and receive UART data
- Support additional functionality of RS232 and GPIO
- Full duplex operation
- Fully configurable serial interface
|
- SystemVerilog Source Code
- User Guide and Release Notes
- Sanity Testcases
- Test Plan + Coverage Plan [Upon Request]
- Examples on topological usage
- Sample Verification Environmenttion
Thank you for your request.
Your submission has been successful. Kindly refresh you inbox to receive our latest document.
Please feel free to contact us.
Follow us on twitter
--
Regards,
Sibridge Technologies
|
|
India Office
301 Shivalik II, Above ICICI Bank,
132 Ft. Ring Road, Satellite,
Ahmedabad- 380015, Gujarat, India.
Phone: +91-79-4006 7637
Fax: +91-79-40067635
Email: info@sibridgetech.com
|
U.S.A. Office
2350 Mission College Blvd.,
Suite 1070, Santa Clara,
CA 95054
Phone: +1-510 -279-3755
Fax: +1-510-225-1775
Email: info@sibridgetech.com
|
|