The SPI Verification IP is a simple solution for verification of SPI master and slave devices. The provided SPI verification package includes master and slave SystemVerilog verification IPs and examples. It will help engineers to quickly create verification environment end test their SPI master and slave devices. 

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Features

• Free SystemVerilog source code
• Easy integration and usage
• Supports SPI bus specification as defined in M68HC11 user manual rev 5.0
• Operates as a Master or Slave
• Supports multiple slaves
• Supports clock polarity selections
• Supports CPHA selection
• Supports both MSB and LSB data transmissions
• Fully configurable and accurate bus timing
• Supports single and burst transfers
• Supports different burst sizes
• Supports wait states injection