PCI Express Verification IP
Overview:

The Sibridge PCI Express (PCIE) Verification IP is a reusable, configurable, pre-verified, plug-and-play verification component developed in System Verilog. It offers an easy to use and complete verification solution for SoCs incorporating PCI Express Endpoints, Root Complex, or Switch at module, chip and system level.



Features:
  • Complaint to PCIe 1.1, 2.0 and 3.0 specifications
  • Supports x1, x2, x4, x8, x12, x16, x32 lanes
  • Support Endpoint, Root Complex, Switch, PCIE to PCI/PCIX Bridge devices’ ports verification
  • Complaint to PIPE 8/16/32 specification


 


  • SystemVerilog Source Code
  • User Guide and Release Notes
  • Sanity Testcases
  • Test Plan + Coverage Plan [Upon Request]
  • Examples on topological usage
  • Sample Verification Environmenttion