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I2C Verification IP
Overview:

The Sibridge Inter-Integrated Circuit (I2C) Verification IP is a reusable, configurable, pre-verified, plug-and-play verification component developed in SystemVerilog. It offers an easy to use and complete verification solution for SoCs incorporating I2C in either Master or Slave or Master-Slave mode at module, chip and system level. 



Features:
  • Supports 100M/1G/10G Ethernet Speeds
  • Fully compliant to I2C Specification Version 2.1 - 2000
  • Supports all types of I2C devices:
    • Master
    • Slave
    • Master and Slave
  • Supports all types of mode:
    • Standard Mode
    • Fast Mode
    • High-Speed Mode
  • Supports 7 and 10 bit addressing
  • Supports start byte handling & clock stretching



 


  • SystemVerilog Source Code
  • User Guide and Release Notes
  • Sanity Testcases
  • Test Plan + Coverage Plan [Upon Request]
  • Examples on topological usage
  • Sample Verification Environmenttion