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Overview:
The SI-MI2Cv2 provides an interface between a microprocessor and an I2C bus that conforms to V2.1 of the I2C bus specification. It can be programmed to operate as either a master or a slave device and performs arbitration in master mode to allow it to operate in multi-master systems.
Features:
- Conforms to V2.1 of the I2C bus specification
- Supports High speed (3400kbits/s), Fast and Standard transfer rates
- Supports bus isolation
- Master or slave operation
- Multi-master systems supported
- Supports both 7-bit and 10-bit addressing on the I2C bus
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- Verilog Source code with lint checking
- Verilog functional testbench and associated documentation
- Design documentation
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