AMBA2 AHB/APB Verification IP
The AMBA Peripheral Bus (APB) Verification IP described here is Verification IP (VIP) written on SystemVerilog for verifying a DUT with AMBA3.0 compliant APB interface. The APB Master Verification IP doesn’t support multiple slaves. For testing multiple APB slave devices the external multiplexor should be used.
- Compliant to AMBA2 AHB specification
- Supports AHB-lite topology
- Supports single/multi Master and Slave verification
- Supports Arbiter and Decoder verification
- Easy to use.
- Configurable APB data size.
- Data word transfer.
- Data buffer transfer.
- Misaligned transfers.
- Configurable valid pready detection.
- Fixed timing delays.
- Random timing delays.
- Slave error detection.
- Error buffer to hold all failed transactions, Slave errors and time outs.
|
- SystemVerilog Source Code
- User Guide and Release Notes
- Sanity Testcases
- Test Plan + Coverage Plan [Upon Request]
- Examples on topological usage
- Sample Verification Environmenttion
Thank you for your request.
Your submission has been successful. Kindly refresh you inbox to receive our latest document.
Please feel free to contact us.
Follow us on twitter
--
Regards,
Sibridge Technologies
|
|
India Office
301 Shivalik II, Above ICICI Bank,
132 Ft. Ring Road, Satellite,
Ahmedabad- 380015, Gujarat, India.
Phone: +91-79-4006 7637
Fax: +91-79-40067635
Email: info@sibridgetech.com
|
U.S.A. Office
2350 Mission College Blvd.,
Suite 1070, Santa Clara,
CA 95054
Phone: +1-510 -279-3755
Fax: +1-510-225-1775
Email: info@sibridgetech.com
|
|